000 04048nam a22005295i 4500
001 978-1-4899-7797-7
003 DE-He213
005 20200420220221.0
007 cr nn 008mamaa
008 161130s2016 xxu| s |||| 0|eng d
020 _a9781489977977
_9978-1-4899-7797-7
024 7 _a10.1007/978-1-4899-7797-7
_2doi
050 4 _aTK7895.M5
072 7 _aUYF
_2bicssc
072 7 _aCOM011000
_2bisacsh
082 0 4 _a004.1
_223
100 1 _aAiken, Alex.
_eauthor.
245 1 0 _aInstruction Level Parallelism
_h[electronic resource] /
_cby Alex Aiken, Utpal Banerjee, Arun Kejariwal, Alexandru Nicolau.
264 1 _aBoston, MA :
_bSpringer US :
_bImprint: Springer,
_c2016.
300 _aXXI, 255 p. 78 illus., 30 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aIntroduction -- Overview of ILP Architectures -- Scheduling Basic Blocks -- Trace Scheduling -- Percolation Scheduling -- Modulo Scheduling -- Software Pipelining by Kernal Recognition -- Epilogue.
520 _aSince its introduction decades ago, Instruction Level Parallelism (ILP) has gradually become ubiquitous and is now featured in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors. Because these architectures could not exist or (in the case of superscalar machines) cannot achieve their full potential without specific sophisticated compilation techniques to exploit ILP, the development of architectures that support ILP has proceeded hand-in-hand with the development of sophisticated compiler technology, such as Trace Scheduling and Software Pipelining. While essential for achieving the full potential of ILP, in both performance as well as power consumption management, these techniques are still not widely known, in part because of their intricacy and in part because the only widely available references for ILP techniques are the primary resources, with the brevity of introduction common to conference proceedings. This book precisely formulates, and simplifies the presentation of Instruction Level Parallelism (ILP) compilation techniques. It uniquely offers consistent and uniform descriptions of the code transformations involved. Due to the ubiquitous nature of ILP in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors, this book is useful to the student, the practitioner and also the researcher of advanced compilation techniques. With an emphasis on fine-grain instruction level parallelism, this book will also prove interesting to researchers and students of parallelism at large, in as much as the techniques described yield insights that go beyond superscalar and VLIW (Very Long Instruction Word) machines compilation and are more widely applicable to optimizing compilers in general. ILP techniques have found wide and crucial application in Design Automation, where they have been used extensively in the optimization of performance as well as area and power minimization of computer designs.
650 0 _aComputer science.
650 0 _aComputer software
_xReusability.
650 0 _aMicroprocessors.
650 0 _aProgramming languages (Electronic computers).
650 0 _aElectrical engineering.
650 1 4 _aComputer Science.
650 2 4 _aProcessor Architectures.
650 2 4 _aCommunications Engineering, Networks.
650 2 4 _aProgramming Languages, Compilers, Interpreters.
650 2 4 _aPerformance and Reliability.
700 1 _aBanerjee, Utpal.
_eauthor.
700 1 _aKejariwal, Arun.
_eauthor.
700 1 _aNicolau, Alexandru.
_eauthor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9781489977953
856 4 0 _uhttp://dx.doi.org/10.1007/978-1-4899-7797-7
912 _aZDB-2-SCS
942 _cEBK
999 _c51926
_d51926