Advances in Computer Systems Architecture (Record no. 89400)
[ view plain ]
000 -LEADER | |
---|---|
fixed length control field | 10169nam a22006495i 4500 |
001 - CONTROL NUMBER | |
control field | 978-3-540-32108-8 |
003 - CONTROL NUMBER IDENTIFIER | |
control field | DE-He213 |
005 - DATE AND TIME OF LATEST TRANSACTION | |
control field | 20240730174356.0 |
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
fixed length control field | cr nn 008mamaa |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 100322s2005 gw | s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
International Standard Book Number | 9783540321088 |
-- | 978-3-540-32108-8 |
024 7# - OTHER STANDARD IDENTIFIER | |
Standard number or code | 10.1007/11572961 |
Source of number or code | doi |
050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
Classification number | QA76.9.S88 |
072 #7 - SUBJECT CATEGORY CODE | |
Subject category code | UYD |
Source | bicssc |
072 #7 - SUBJECT CATEGORY CODE | |
Subject category code | COM011000 |
Source | bisacsh |
072 #7 - SUBJECT CATEGORY CODE | |
Subject category code | UYD |
Source | thema |
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
Classification number | 004.2 |
Edition number | 23 |
245 10 - TITLE STATEMENT | |
Title | Advances in Computer Systems Architecture |
Medium | [electronic resource] : |
Remainder of title | 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings / |
Statement of responsibility, etc. | edited by Thambipillai Srikanthan, Jingling Xue, Chip-Hong Chang. |
250 ## - EDITION STATEMENT | |
Edition statement | 1st ed. 2005. |
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
Place of production, publication, distribution, manufacture | Berlin, Heidelberg : |
Name of producer, publisher, distributor, manufacturer | Springer Berlin Heidelberg : |
-- | Imprint: Springer, |
Date of production, publication, distribution, manufacture, or copyright notice | 2005. |
300 ## - PHYSICAL DESCRIPTION | |
Extent | XVIII, 834 p. |
Other physical details | online resource. |
336 ## - CONTENT TYPE | |
Content type term | text |
Content type code | txt |
Source | rdacontent |
337 ## - MEDIA TYPE | |
Media type term | computer |
Media type code | c |
Source | rdamedia |
338 ## - CARRIER TYPE | |
Carrier type term | online resource |
Carrier type code | cr |
Source | rdacarrier |
347 ## - DIGITAL FILE CHARACTERISTICS | |
File type | text file |
Encoding format | |
Source | rda |
490 1# - SERIES STATEMENT | |
Series statement | Theoretical Computer Science and General Issues, |
International Standard Serial Number | 2512-2029 ; |
Volume/sequential designation | 3740 |
505 0# - FORMATTED CONTENTS NOTE | |
Formatted contents note | Keynote Address I -- Processor Architecture for Trustworthy Computers -- Session 1A: Energy Efficient and Power Aware Techniques -- Efficient Voltage Scheduling and Energy-Aware Co-synthesis for Real-Time Embedded Systems -- Energy-Effective Instruction Fetch Unit for Wide Issue Processors -- Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty -- An Innovative Instruction Cache for Embedded Processors -- Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) Processor -- Session 1B: Methodologies and Architectures for Application-Specific Systems -- Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution -- A Pipelined Hardware Architecture for Motion Estimation of H.264/AVC -- Embedded Intelligent Imaging On-Board Small Satellites -- Architectural Enhancements for Color Image and Video Processing on Embedded Systems -- A Portable Doppler Device Based on a DSP with High- Performance Spectral Estimation and Output -- Session 2A: Processor Architectures and Microarchitectures -- A Power-Efficient Processor Core for Reactive Embedded Applications -- A Stream Architecture Supporting Multiple Stream Execution Models -- The Challenges of Massive On-Chip Concurrency -- FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit -- Session 2B: High-Reliability and Fault-Tolerant Architectures -- Modularized Redundant Parallel Virtual File System -- Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures -- A Fault-Tolerant Routing Strategy for Fibonacci-Class Cubes -- Embedding of Cycles in the Faulty Hypercube -- Session 3A: Compiler and OS for Emerging Architectures -- Improving the Performance of GCC by Exploiting IA-64 Architectural Features -- An Integrated Partitioning and Scheduling Based Branch Decoupling -- A Register Allocation Framework for Banked Register Files with Access Constraints -- Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems -- Irregular Redistribution Scheduling by Partitioning Messages -- Session 3B: Data Value Predictions -- Making Power-Efficient Data Value Predictions -- Speculative Issue Logic -- Using Decision Trees to Improve Program-Based and Profile-Based Static Branch Prediction -- Arithmetic Data Value Speculation -- Exploiting Thread-Level Speculative Parallelism with Software Value Prediction -- Keynote Address II -- Challenges and Opportunities on Multi-core Microprocessor -- Session 4A: Reconfigurable Computing Systems and Polymorphic Architectures -- Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures -- A Switch Wrapper Design for SNA On-Chip-Network -- A Configuration System Architecture Supporting Bit-Stream Compression for FPGAs -- Biological Sequence Analysis with Hidden Markov Models on an FPGA -- FPGAs for Improved Energy Efficiency in Processor Based Systems -- Morphable Structures for Reconfigurable Instruction Set Processors -- Session 4B: Interconnect Networks and Network Interfaces -- Implementation of a Hybrid TCP/IP Offload Engine Prototype -- Matrix-Star Graphs: A New Interconnection Network Based on Matrix Operations -- The Channel Assignment Algorithm on RP(k) Networks -- Extending Address Space of IP Networks with Hierarchical Addressing -- The Star-Pyramid Graph: An Attractive Alternative to the Pyramid -- Building a Terabit Router with XD Networks -- Session 5A: Parallel Architectures and Computation Models -- A Real Coded Genetic Algorithm for Data Partitioning and Scheduling in Networks with Arbitrary Processor Release Time -- D3DPR: A Direct3D-Based Large-Scale Display Parallel Rendering System Architecture for Clusters -- Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures -- A Technique to Reduce Preemption Overhead in Real-Time Multiprocessor Task Scheduling -- Session 5B: Hardware-Software Partitioning, Verification, and Testing of Complex Architectures -- Minimizing Power in Hardware/Software Partitioning -- Exploring Design Space Using Transaction Level Models -- Increasing Embedding Probabilities of RPRPs in RIN Based BIST -- A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture -- Session 6A: Architectures for Secured Computing -- DRIL- A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding Techniques -- Efficient Architectural Support for Secure Bus-Based Shared Memory Multiprocessor -- Covert Channel Analysis of the Password-Capability System -- Session 6B: Simulation and Performance Evaluation -- Comparing Low-Level Behavior of SPEC CPU and Java Workloads -- Application of Real-Time Object-Oriented Modeling Technique for Real-Time Computer Control -- VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers -- Session 7: Architectures for Emerging Technologies and Applications I -- Analysis of Real-Time Communication System with Queuing Priority -- FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks -- A Study on the Performance Evaluation of Forward Link in CDMA Mobile Communication Systems -- Session 8: Memory Systems Hierarchy and Management -- Cache Leakage Management for Multi-programming Workloads -- A Memory Bandwidth Effective Cache Store Miss Policy -- Application-SpecificHardware-Driven Prefetching to Improve Data Cache Performance -- Targeted Data Prefetching -- Session 9: Architectures for Emerging Technologies and Applications II -- Area-Time Efficient Systolic Architecture for the DCT -- Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform -- A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures -- Implementation and Analysis of TCP/IP Offload Engine and RDMA Transfer Mechanisms on an Embedded System. |
520 ## - SUMMARY, ETC. | |
Summary, etc. | On behalf of the ProgramCommittee, we are pleased to present the proceedings of the 2005 Asia-Paci?c Computer Systems Architecture Conference (ACSAC 2005) held in the beautiful and dynamic country of Singapore. This conference was the tenth in its series, one of the leading forums for sharing the emerging research ?ndings in this ?eld. In consultation with the ACSAC Steering Committee, we selected a - member Program Committee. This Program Committee represented a broad spectrum of research expertise to ensure a good balance of research areas, - stitutions and experience while maintaining the high quality of this conference series. This year's committee was of the same size as last year but had 19 new faces. We received a total of 173 submissions which is 14% more than last year. Each paper was assigned to at least three and in some cases four ProgramC- mittee members for review. Wherever necessary, the committee members called upon the expertise of their colleagues to ensure the highest possible quality in the reviewing process. As a result, we received 415 reviews from the Program Committee members and their 105 co-reviewers whose names are acknowledged inthe proceedings.Theconferencecommitteeadopteda systematicblind review process to provide a fair assessment of all submissions. In the end, we accepted 65 papers on a broad range of topics giving an acceptance rate of 37.5%. We are grateful to all the Program Committee members and the co-reviewers for their e?orts in completing the reviews within a tight schedule. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name entry element | Computer systems. |
9 (RLIN) | 112253 |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name entry element | Computer arithmetic and logic units. |
9 (RLIN) | 36750 |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name entry element | Computer input-output equipment. |
9 (RLIN) | 22942 |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name entry element | Logic design. |
9 (RLIN) | 3686 |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name entry element | Computer networks . |
9 (RLIN) | 31572 |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name entry element | Microprocessors. |
9 (RLIN) | 112254 |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name entry element | Computer architecture. |
9 (RLIN) | 3513 |
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name entry element | Computer System Implementation. |
9 (RLIN) | 38514 |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name entry element | Arithmetic and Logic Structures. |
9 (RLIN) | 36752 |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name entry element | Input/Output and Data Communications. |
9 (RLIN) | 37326 |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name entry element | Logic Design. |
9 (RLIN) | 3686 |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name entry element | Computer Communication Networks. |
9 (RLIN) | 112255 |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name entry element | Processor Architectures. |
9 (RLIN) | 112256 |
700 1# - ADDED ENTRY--PERSONAL NAME | |
Personal name | Srikanthan, Thambipillai. |
Relator term | editor. |
Relationship | edt |
-- | http://id.loc.gov/vocabulary/relators/edt |
9 (RLIN) | 112257 |
700 1# - ADDED ENTRY--PERSONAL NAME | |
Personal name | Xue, Jingling. |
Relator term | editor. |
Relationship | edt |
-- | http://id.loc.gov/vocabulary/relators/edt |
9 (RLIN) | 112258 |
700 1# - ADDED ENTRY--PERSONAL NAME | |
Personal name | Chang, Chip-Hong. |
Relator term | editor. |
Relationship | edt |
-- | http://id.loc.gov/vocabulary/relators/edt |
9 (RLIN) | 112259 |
710 2# - ADDED ENTRY--CORPORATE NAME | |
Corporate name or jurisdiction name as entry element | SpringerLink (Online service) |
9 (RLIN) | 112260 |
773 0# - HOST ITEM ENTRY | |
Title | Springer Nature eBook |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
Relationship information | Printed edition: |
International Standard Book Number | 9783540296430 |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
Relationship information | Printed edition: |
International Standard Book Number | 9783540817208 |
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
Uniform title | Theoretical Computer Science and General Issues, |
International Standard Serial Number | 2512-2029 ; |
Volume/sequential designation | 3740 |
9 (RLIN) | 112261 |
856 40 - ELECTRONIC LOCATION AND ACCESS | |
Uniform Resource Identifier | <a href="https://doi.org/10.1007/11572961">https://doi.org/10.1007/11572961</a> |
912 ## - | |
-- | ZDB-2-SCS |
912 ## - | |
-- | ZDB-2-SXCS |
912 ## - | |
-- | ZDB-2-LNC |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Koha item type | eBooks-Lecture Notes in CS |
No items available.