Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip (Record no. 77704)
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000 -LEADER | |
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fixed length control field | 04150nam a22005895i 4500 |
001 - CONTROL NUMBER | |
control field | 978-3-319-60402-2 |
005 - DATE AND TIME OF LATEST TRANSACTION | |
control field | 20220801215635.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 170706s2018 sz | s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
ISBN | 9783319604022 |
-- | 978-3-319-60402-2 |
082 04 - CLASSIFICATION NUMBER | |
Call Number | 621.3815 |
100 1# - AUTHOR NAME | |
Author | Meinerzhagen, Pascal. |
245 10 - TITLE STATEMENT | |
Title | Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip |
250 ## - EDITION STATEMENT | |
Edition statement | 1st ed. 2018. |
300 ## - PHYSICAL DESCRIPTION | |
Number of Pages | IX, 146 p. 84 illus. in color. |
505 0# - FORMATTED CONTENTS NOTE | |
Remark 2 | Motivation -- Introduction to Gain-Cell Based eDRAMs (GC-eDRAMs) -- GC-eDRAMs Operated at Scaled Supply Voltages -- Near-VT GC-eDRAM Implementations with Extended Retention Times -- Aggressive Technology and Voltage Scaling (to Sub-VT Domain) -- Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications -- 4T Gain-Cell with Internal-Feedback for Ultra-Low Retention Power at Scaled CMOS Nodes -- Multilevel GC-eDRAM (MLGC-eDRAM) -- Soft Error Tolerant Low Power 4T Gain-Cell Array with Multi-Bit Error Detection and Correction -- Conclusions. |
520 ## - SUMMARY, ETC. | |
Summary, etc | This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy. |
700 1# - AUTHOR 2 | |
Author 2 | Teman, Adam. |
700 1# - AUTHOR 2 | |
Author 2 | Giterman, Robert. |
700 1# - AUTHOR 2 | |
Author 2 | Edri, Noa. |
700 1# - AUTHOR 2 | |
Author 2 | Burg, Andreas. |
700 1# - AUTHOR 2 | |
Author 2 | Fish, Alexander. |
856 40 - ELECTRONIC LOCATION AND ACCESS | |
Uniform Resource Identifier | https://doi.org/10.1007/978-3-319-60402-2 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Koha item type | eBooks |
264 #1 - | |
-- | Cham : |
-- | Springer International Publishing : |
-- | Imprint: Springer, |
-- | 2018. |
336 ## - | |
-- | text |
-- | txt |
-- | rdacontent |
337 ## - | |
-- | computer |
-- | c |
-- | rdamedia |
338 ## - | |
-- | online resource |
-- | cr |
-- | rdacarrier |
347 ## - | |
-- | text file |
-- | |
-- | rda |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Electronic circuits. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Computer storage devices. |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Memory management (Computer science). |
650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Electronics. |
650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Electronic Circuits and Systems. |
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Computer Memory Structure. |
650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
-- | Electronics and Microelectronics, Instrumentation. |
912 ## - | |
-- | ZDB-2-ENG |
912 ## - | |
-- | ZDB-2-SXE |
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