High performance switches and routers / (Record no. 59319)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 07833nam a2201141 i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 5236680 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200421114110.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 071029t20152007njua ob 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9780470113950 |
| -- | electronic |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| -- | paper |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| -- | electronic |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.38216 |
| 100 1# - AUTHOR NAME | |
| Author | Chao, H. Jonathan, |
| 245 10 - TITLE STATEMENT | |
| Title | High performance switches and routers / |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | 1 PDF (1 online resource (xviii, 613 pages)) : |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | PREFACE -- ACKNOWLEDGMENTS -- 1 INTRODUCTION -- 1.1 Architecture of the Internet: Present and Future -- 1.2 Router Architectures -- 1.3 Commercial Core Router Examples -- 1.4 Design of Core Routers -- 1.5 IP Network Management -- -- 1.6 Outline of the Book -- 2 IP ADDRESS LOOKUP -- 2.1 Overview -- 2.2 Trie-Based Algorithms -- 2.3 Hardware-Based Schemes -- 2.4 IPv6 Lookup -- 2.5 Comparison -- 3 PACKET CLASSIFICATION -- 3.1 Introduction -- 3.2 Trie-Based Classifications -- 3.3 Geometric Algorithms -- 3.4 Heuristic Algorithms -- 3.5 TCAM-Based Algorithms -- 4 TRAFFIC MANAGEMENT -- 4.1 Quality of Service -- 4.2 Integrated Services -- 4.3 Differentiated Services -- 4.4 Traffic Policing and Shaping -- 4.5 Packet Scheduling -- 4.6 Buffer Management -- 5 BASICS OF PACKET SWITCHING -- 5.1 Fundamental Switching Concept -- 5.2 Switch Fabric Classification -- 5.3 Buffering Strategy in Switching Fabrics -- 5.4 Multiplane Switching and Multistage Switching -- 5.5 Performance of Basic Switches -- 6 SHARED-MEMORY SWITCHES -- 6.1 Linked List Approach -- 6.2 Content Addressable Memory Approach -- 6.3 Space-Time-Space Approach -- 6.4 Scaling the Shared-Memory Switches -- 6.5 Multicast Shared-Memory Switches -- 7 INPUT-BUFFERED SWITCHES -- 7.1 Scheduling in VOQ-Based Switches -- 7.2 Maximum Matching -- 7.3 Maximal Matching -- 7.4 Randomized Matching Algorithms -- 7.5 Frame-based Matching -- 7.6 Stable Matching with Speedup -- 8 BANYAN-BASED SWITCHES -- 8.1 Banyan Networks -- 8.2 Batcher-Sorting Network -- 8.3 Output Contention Resolution Algorithms -- 8.4 The Sunshine Switch -- 8.5 Deflection Routing -- 8.6 Multicast Copy Networks -- 9 KNOCKOUT-BASED SWITCHES -- 9.1 Single-Stage Knockout Switch -- 9.2 Channel Grouping Principle -- 9.3 Two-Stage Multicast Output-Buffered ATM Switch (MOBAS) -- 9.4 Appendix -- 10 THE ABACUS SWITCH -- 10.1 Basic Architecture -- 10.2 Multicast Contention Resolution Algorithm -- 10.3 Implementation of Input Port Controller. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Remark 2 | 10.4 Performance -- 10.5 ATM Routing and Concentration (ARC) Chip -- 10.6 Enhanced Abacus Switch -- 10.7 Abacus Switch for Packet Switching -- 11 CROSSPOINT BUFFERED SWITCHES -- 11.1 Combined Input and Crosspoint Buffered Switches -- 11.2 Combined Input and Crosspoint Buffered Switches with VOQ -- 11.3 OCF_OCF: Oldest Cell First Scheduling -- 11.4 LQF_RR: Longest Queue First and Round-Robin Scheduling in CIXB-1 -- 11.5 MCBF: Most Critical Buffer First Scheduling -- 12 CLOS-NETWORK SWITCHES -- 12.1 Routing Property of Clos Network Switches -- 12.2 Looping Algorithm -- 12.3 m-Matching Algorithm -- 12.4 Euler Partition Algorithm -- 12.5 Karol's Algorithm -- 12.6 Frame-Based Matching Algorithm for Clos Network (f-MAC) -- 12.7 Concurrent Matching Algorithm for Clos Network (c-MAC) -- 12.8 Dual-Level Matching Algorithm for Clos Network (d-MAC) -- 12.9 The ATLANTA Switch -- 12.10 Concurrent Round-Robin Dispatching (CRRD) Scheme -- 12.11 The Path Switch -- 13 MULTI-PLANE MULTI-STAGE BUFFERED SWITCH -- 13.1 TrueWay Switch Architecture -- 13.2 Packet Scheduling -- 13.3 Stage-To-Stage Flow Control -- 13.4 Port-To-Port Flow Control -- 13.5 Performance Analysis -- 13.6 Prototype -- 14 LOAD-BALANCED SWITCHES -- 14.1 Birkhoff-Von Neumann Switch -- 14.2 Load-Balanced Birkhoff-von Neumann Switches -- 14.3 Load-Balanced Birkhoff-von Neumann SwitchesWith FIFO Service -- 15 OPTICAL PACKET SWITCHES -- 15.1 Opto-Electronic Packet Switches -- 15.2 Optoelectronic Packet Switch Case Study I -- 15.3 Optoelectronic Packet Switch Case Study II -- 15.4 All Optical Packet Switches -- 15.5 Optical Packet Switch with Shared Fiber Delay Lines Single-stage Case -- 15.6 All Optical Packet Switch with Shared Fiber Delay Lines - Three Stage Case -- 16 HIGH-SPEED ROUTER CHIP SET -- 16.1 Network Processors (NPs) -- 16.2 Co-Processors for Packet Classification -- 16.3 Traffic Management Chips -- 16.4 Switching Fabric Chips -- INDEX. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | As Internet traffic grows and demands for quality of service become stringent, researchers and engineers can turn to this go-to guide for tested and proven solutions. This text presents the latest developments in high performance switches and routers, coupled with step-by-step design guidance and more than 550 figures and examples to enable readers to grasp all the theories and algorithms used for design and implementation. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Liu, Bin. |
| 856 42 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5236680 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Hoboken, New Jersey : |
| -- | Wiley-Interscience, |
| -- | c2007. |
| 336 ## - | |
| -- | text |
| -- | rdacontent |
| 337 ## - | |
| -- | electronic |
| -- | isbdmedia |
| 338 ## - | |
| -- | online resource |
| -- | rdacarrier |
| 588 ## - | |
| -- | Description based on PDF viewed 12/19/2015. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Asynchronous transfer mode. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Routers (Computer networks) |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer network protocols. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Packet switching (Data transmission) |
| 695 ## - | |
| -- | Admission control |
| 695 ## - | |
| -- | Bandwidth |
| 695 ## - | |
| -- | Bipartite graph |
| 695 ## - | |
| -- | Buffer storage |
| 695 ## - | |
| -- | Classification algorithms |
| 695 ## - | |
| -- | Color |
| 695 ## - | |
| -- | Complexity theory |
| 695 ## - | |
| -- | Computer aided manufacturing |
| 695 ## - | |
| -- | Computer architecture |
| 695 ## - | |
| -- | Data structures |
| 695 ## - | |
| -- | Degradation |
| 695 ## - | |
| -- | Delay |
| 695 ## - | |
| -- | Fabrics |
| 695 ## - | |
| -- | Hardware |
| 695 ## - | |
| -- | IP networks |
| 695 ## - | |
| -- | Indexes |
| 695 ## - | |
| -- | Integrated circuit interconnections |
| 695 ## - | |
| -- | Internet |
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| -- | Matrix decomposition |
| 695 ## - | |
| -- | Memory management |
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| -- | Microprocessors |
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| -- | Multiplexing |
| 695 ## - | |
| -- | Multiprocessor interconnection |
| 695 ## - | |
| -- | Multiprotocol label switching |
| 695 ## - | |
| -- | Optical buffering |
| 695 ## - | |
| -- | Optical packet switching |
| 695 ## - | |
| -- | Optical receivers |
| 695 ## - | |
| -- | Optical switches |
| 695 ## - | |
| -- | Optical transmitters |
| 695 ## - | |
| -- | Organizations |
| 695 ## - | |
| -- | Packet switching |
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| -- | Parallel processing |
| 695 ## - | |
| -- | Partitioning algorithms |
| 695 ## - | |
| -- | Probability |
| 695 ## - | |
| -- | Processor scheduling |
| 695 ## - | |
| -- | Program processors |
| 695 ## - | |
| -- | Quality of service |
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| -- | Random access memory |
| 695 ## - | |
| -- | Real time systems |
| 695 ## - | |
| -- | Registers |
| 695 ## - | |
| -- | Routing |
| 695 ## - | |
| -- | Routing protocols |
| 695 ## - | |
| -- | Scalability |
| 695 ## - | |
| -- | Schedules |
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| -- | Scheduling algorithm |
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| -- | Sections |
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| -- | Software algorithms |
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| -- | Sorting |
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| -- | Switches |
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| -- | Switching circuits |
| 695 ## - | |
| -- | Throughput |
| 695 ## - | |
| -- | Time division multiplexing |
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