Instruction Level Parallelism (Record no. 51926)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 04048nam a22005295i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-1-4899-7797-7 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200420220221.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 161130s2016 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781489977977 |
| -- | 978-1-4899-7797-7 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 004.1 |
| 100 1# - AUTHOR NAME | |
| Author | Aiken, Alex. |
| 245 10 - TITLE STATEMENT | |
| Title | Instruction Level Parallelism |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XXI, 255 p. 78 illus., 30 illus. in color. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Introduction -- Overview of ILP Architectures -- Scheduling Basic Blocks -- Trace Scheduling -- Percolation Scheduling -- Modulo Scheduling -- Software Pipelining by Kernal Recognition -- Epilogue. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | Since its introduction decades ago, Instruction Level Parallelism (ILP) has gradually become ubiquitous and is now featured in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors. Because these architectures could not exist or (in the case of superscalar machines) cannot achieve their full potential without specific sophisticated compilation techniques to exploit ILP, the development of architectures that support ILP has proceeded hand-in-hand with the development of sophisticated compiler technology, such as Trace Scheduling and Software Pipelining. While essential for achieving the full potential of ILP, in both performance as well as power consumption management, these techniques are still not widely known, in part because of their intricacy and in part because the only widely available references for ILP techniques are the primary resources, with the brevity of introduction common to conference proceedings. This book precisely formulates, and simplifies the presentation of Instruction Level Parallelism (ILP) compilation techniques. It uniquely offers consistent and uniform descriptions of the code transformations involved. Due to the ubiquitous nature of ILP in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors, this book is useful to the student, the practitioner and also the researcher of advanced compilation techniques. With an emphasis on fine-grain instruction level parallelism, this book will also prove interesting to researchers and students of parallelism at large, in as much as the techniques described yield insights that go beyond superscalar and VLIW (Very Long Instruction Word) machines compilation and are more widely applicable to optimizing compilers in general. ILP techniques have found wide and crucial application in Design Automation, where they have been used extensively in the optimization of performance as well as area and power minimization of computer designs. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Reusability. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Banerjee, Utpal. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Kejariwal, Arun. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Nicolau, Alexandru. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-1-4899-7797-7 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Boston, MA : |
| -- | Springer US : |
| -- | Imprint: Springer, |
| -- | 2016. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer science. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer software |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Programming languages (Electronic computers). |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electrical engineering. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer Science. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Communications Engineering, Networks. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Programming Languages, Compilers, Interpreters. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Performance and Reliability. |
| 912 ## - | |
| -- | ZDB-2-SCS |
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